//======================================================================
//    We will gone,the word kept  
//======================================================================
//write data'width = read data width xN
`timescale 1ns / 1ps

module dpram1w1r_mtird#(
    parameter WR_NUMBIT = 8,                    // wr data width :rd data width  (in mulrd,write data width bigger),
    parameter RAM_WIDTH = 32,                   // Specify RAM data width,wr data width
    parameter RAM_DEPTH = 1024,                 // Specify RAM depth (number of entries)
    parameter RAM_STYLE = "auto" ,             // default: auto, "distributed" or "block"
    parameter OUTREG_EN = "FALSE",              // Select "FALSE" or "TURE" 
    parameter INIT_FILE = ""                    // Specify name/location of RAM initialization file if using one (leave blank if not)
) (
    input [clogb2(RAM_DEPTH-1)-1:0] addra, // Write address bus, width determined from RAM_DEPTH
    input [clogb2(RAM_DEPTH-1)-1:0] addrb, // Read address bus, width determined from RAM_DEPTH
    input [RAM_WIDTH-1:0]           dina,          // RAM input data
    input clka,                          // Clock
    input clkb,                         // Clock
    input                     wea,                           // Write enable
    input [WR_NUMBIT-1:0]     enb,                           // Read Enable, for additional power savings, disable when not in use
    //input rstn,                          // resetn (does not affect memory contents)
    //input regceb,                        // register enable
    output [RAM_WIDTH*WR_NUMBIT-1:0] doutb         // RAM output data
);
genvar i ;
    generate
    for(i=0; i<WR_NUMBIT; i=i+1) begin:BLOCK1
                dpram1w1r #(
	            .RAM_WIDTH (DATA_WIDTH),
	            .RAM_DEPTH (RAM_DEPTH),
                .RAM_STYLE (RAM_STYLE),
                .OUTREG_EN (OUTREG_EN),
                .INIT_FILE (INIT_FILE)
            ) u_ram
            (
	         	.clka       (wr_clk ) ,
	         	.wea	    (wea   ) ,
	         	.addra      (addra )  ,
	         	.dina       (din )    ,
	         	.clkb       (rd_clk ) ,
	         	.enb	     (enb[i] ),
	         	.addrb      (addrb) ,
	         	.doutb      (dout[(i*RAM_WIDTH+RAM_WIDTH-1)-:RAM_WIDTH] ) 
	         	);
			 end
    endgenerate
    
    //  The following function calculates the address width based on specified RAM depth
    function integer clogb2;
    input integer depth;
        for (clogb2=0; depth>0; clogb2=clogb2+1)
        depth = depth >> 1;
    endfunction

endmodule
